Integrated circuits (ICs), such as ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETs). The transistors can include semiconductor gates disposed between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (e.g., boron) or an N-type dopant (e.g., phosphorous or arsenic).
The source and drain regions generally include a thin extension that is disposed partially underneath the gate to enhance transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-inducted barrier lowering. Controlling short-channel effects is particularly important as transistors become smaller.
Conventional techniques utilize a double implant process to form deeper source and drain regions and shallow source and drain extensions. According to the conventional process, source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate. The silicon substrate is doped on both sides of the gate structure via a conventional doping process such as a thermal diffusion process or an ion implantation process. Without the sidewall spacers, the doping process introduces dopants into a thin region (i.e., just below the top surface of the substrate) to form the source and drain extensions, as well as to partially form the source and drain regions.
After the source and drain extensions are formed, silicon dioxide or silicon nitride spacers, which abut lateral sides of the gate structure, are provided over the source and drain extensions. The substrate is doped a second time to form the deeper source and drain regions, which are necessary for proper silicidation. The source and drain extensions are not further doped due to the blocking capability of the silicon dioxide spacer.
SMOS processes are utilized to increase transistor (MOSFET) performance by increasing the carrier mobility of silicon, thereby reducing resistance and power consumption and increasing drive current, frequency response, and operating speed. Strained silicon is typically formed by growing a layer of silicon on a silicon germanium substrate or layer. Germanium can also be implanted, deposited, or otherwise provided to silicon layers to change the lattice structure of the silicon and increase carrier mobility.
The silicon germanium lattice associated with the germanium substrate is generally more widely spaced than a pure silicon lattice, with spacing becoming wider with a higher percentage of germanium. Because the silicon lattice aligns with the larger silicon germanium lattice, a tensile strain is created in the silicon layer. The silicon atoms are essentially pulled apart from one another. Relaxed silicon has a conductive band that contains six equal balance bands. The application of tensile strength to the silicon causes four of the balance bands to increase in energy and two of the balance bands to decrease in energy. As a result of quantum effects, electrons effectively weigh 30 percent less when passing through the lower energy bands. Thus, lower energy bands offer less resistance to electron flow.
In addition, electrons meet with less vibrational energy from the nucleus of the silicon atom, which causes them to scatter at a rate of 500 to 1,000 times less than in relaxed silicon. As a result, carrier mobility is dramatically increased in strained silicon compared to relaxed silicon, providing an increase in mobility of 80 percent or more for electrons and 20 percent or more for holes. The increase in mobility has been found to persist for current fields up to 1.5 megavolt/centimeter. These factors are believed to enable device speed increase of 35 percent without further reduction of device size, or a 25 percent reduction in power consumption without a reduction in performance.
Heretofore, forming source and drain extensions on strained semiconductor layers has been difficult using conventional double implant processes. For example, compensation is required for N-type dopants to reduce enhanced lateral diffusion under the edge of the gate. Enhanced lateral diffusion causes overlap of source and drain extensions in the channel, thereby resulting in short channel effects.
Low annealing temperatures and low thermal budgets are often utilized to reduce short channel effects. However, low annealing temperatures and low thermal budgets can cause suppressed diffusion of P-type dopants in strained silicon. Suppressed boron diffusion can prevent sufficient overlap of the gate and the source and drain regions, thereby resulting in lower drive currents (ld(sat). 
Thus, there is a need for an SMOS process which compensates for the adverse effects of enhanced lateral diffusion of N-type dopants and yet allows sufficient diffusion of P-type dopants. Further still, there is a need for a process optimized to reduce short channel effects associated with diffusion of source and drain extensions. Yet further, there is a need for SMOS transistors that are less susceptible to short channel effects. Even further still, there is a need for an efficient method of fabricating source and drain regions in an SMOS process.